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THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
AUGUST 1992
DS3535 - 1.0
CLA70000V
LOW VOLTAGE SPECIFICATION 1.0 CMOS GATE ARRAYS
FEATURES
s Operates at 3.3V
s
1.0 (0.8 Leff) twin well, epitaxial CMOS process
s
5,000 to 250,000 available gates on a chanelless array architecture
s
Low current and power (<1A/gate/MHz)
s
Slew controlled outputs with drivers up to 12mA for bus driving and other applications.
s
ESD protection in excess of 2kV
s
GENERAL DESCRIPTION
Advances in processing technology have led to the development of an array family which can operate at 3 volts. This series of arrays may be used with the lower voltage power supply rails which are becoming increasingly common. Applications include battery portable such as laptop computers where low power consumption is essential as well as pagers and consumer applications like hand held language translators and games. This summary datasheet gives information on the CLA70000 series AC and DC characteristics at low voltage.
Comprehensive cell library including DSP and compiled memory cells (ROM blocks to 64K bits and RAM blocks to 16K bits)
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Supports JTAG/BIST test philosophies (IEEE 1149-1 Test Procedures)
s
Fully supported on Industry Standard workstations and in-house software
CLA70000 FAMILY
ARRAY CLA70000 CLA71000 CLA72000 CLA73000 CLA74000 CLA75000 CLA76000 CLA77000 CLA78000 RAW GATES 5000 12000 19000 27000 39000 70000 110000 182000 256000 PADS 44 68 84 100 120 160 200 256 304
CONTENTS
Description Process Technology Core Design I/O Design AC Characteristics DC Characteristics Design Tools Packaging Page 2 2 2 3 4 5 6
CLA70000V
CMOS PROCESS TECHNOLOGY
The CLA70000 arrays are based on GEC Plessey Semiconductors well proven 1 CMOS process, manufactured at GPS's advanced , Class 10, six-inch wafer fabrication facility. The process (fig.1) is a twin well, self aligned oxide-isolated technology, with an effective channel length of 0.8m (1.0m drawn ), giving a low defect density, high reliability, and inherently low power dissipation. The process has excellent immunity to latch-up, and ESD, and exhibits stable performance characteristics.
Figure 1 : Process `VQ' Process Cross Section
VSS Supply Supply
VDD
CORE CELL DESIGN
A four transistor group (2 NMOS and 2PMOS) (fig 2.) forms the basic cell of the core array. This array element is repeated in a regular fashion over the complete core area to give a homogeneous `Full Field' (sea of gates) array. This lends itself to hierarchical design, allowing pre-routed user defined subcircuits to be repeated anywhere on the array. The core cell structure has been carefully designed to maximise the number of nets which may be routed through the cell. This enables optimal routing for both data flow and control signal distribution schemes thus giving very high overall utilisation figures. This feature is of particular benefit in designs using highly structured blocks such as memory or arithmetic functions.
Programmable contacts
VSS Supply
Figure 2 : Diagrammatic representation of Array Core Cell
IB1 IB2 IB3 IB4 IB5
INPUT/OUTPUT BUFFER DESIGN
The peripheral cells (fig.3) are fully programmable as Input, Output, VDD or GND, and they are designed to offer several interfacing options, TTL and CMOS for example. The cells already contain input `pull-up' and `pull-down' resistors and Electro Static Discharge protection elements. Components for implementing Schmitt Triggers, TTL threshold detectors, tristate control, and flip-flops for signal re-timing are also included. A range of output buffers is available with various output drive currents to match system requirements. Noise transients due to a large number of simultaneously switching outputs are an increasing problem as bus widths widen (The supply pad location, and the inductance of the bond wires and package leads are also factors). CLA70000 Arrays offer several I/O buffers with the capability to control the output slew (di/dt) (fig.4) which are invaluable in controlling these transients when driving large capacitive loads such as busses.
OP1 IP
OP2
Bonding Pad
I/O BLOCK
Figure 3
SLEW RATE CONTROL
INPUT DATA
D
slew rate controlled driver
P N
P OPT3 N
PIN
50 pF
2.5 Volts
2.5 Volts
IBSK1, IBSK2 and IBSK3 have been characterised to give the correct timing when connected to the OPT* cells.
Figure 4
2
CLA70000V
AC CHARACTERISTICS
The performance of the CLA70000V device depends on numerous factors including:
Supply voltage Ambient temperature, and temperature of the devices active junctions Gate front, i.e. the logic loading on the gate outputs Interconnection loading on the gates Processing tolerance, i.e. the manufacturing spreads The CLA70000 technology library contains all the performance information for each cell in the design libraries. The PDS design software suite accesses this data, and the simulation program automatically calculates the design's performance under the selected operating conditions. Prior to layout, estimates of the interconnection loadings are used in the simulations. After layout, track loadings are extracted from the physical design to allow re-simulation with actual values to confirm device performance. The effect of those factors on the propagation delays of arange of selected cells is illustrated in the tables below.
Fanout is in gate load units
Typical propagation Delay Ns 5 volts 25C Symbol tpLH tpLH NAND2 1 2-INPUT NAND GATE tpHL tpLH NOR2 1 2-INPUT NOR GATE tpLH tpLH DF 4 MASTER SLAVE D-TYPE FLIP FLOP tpHL tpLH Fanout = 2 0.27 0.18 0.39 0.30 0.50 0.22 0.54 0.55 Worst case Propagation Delay (ns) 3 volts 70C Fanout 2 0.95 0.64 1.37 1.07 1.77 0.78 1.90 1.96 4 1.14 0.76 1.75 1.41 2.46 1.09 2.18 2.11
INTERNAL CORE CELLS
Name INV2 Cells 1 Description INVERTER DUAL DRIVE
INTERMEDIATE BUFFER CELLS
Name IBGATE Cells Description LARGE 2 INPUT NAND GATE +2 INPUT NOR Symbol tpLH tpLH IBDF MASTER SLAVE D-TYPE FLIP FLOP tpHL tpLH IBCMOS1 CMOS INPUT BUFFER WITH 2 INPUT NAND GATE tpLH tpLH
Typical propagation Delay Ns 5 volts 25C Fanout = 2 0.34 0.27 0.48 0.50 0.60 0.45
Worst case Propagation Delay (ns) 3 volts 70C Fanout 2 1.20 0.97 1.69 1.78 2.15 1.59 4 1.39 1.14 1.96 1.93 2.28 1.65
OUTPUT BUFFER CELLS
Name OP3 Cells Description STANDARD OUTPUT BUFFER Symbol tpLH tpLH OP6 MEDIUM OUTPUT BUFFER tpHL tpLH OP12 LARGE OUTPUT BUFFER tpLH tpLH
Typical propagation Delay Ns 5 volts 25C Fanout = 10pF 0.73 0.49 0.50 0.33 0.38 0.25
Worst case Propagation Delay (ns) 3 volts 70C Fanout 10pF 2.58 1.73 1.77 1.16 1.35 0.90 50pF 8.83 5.98 4.88 3.29 2.91 2.04
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CLA70000V
DC ELECTRICAL CHARACTERISTICS
All characteristics at 3 - 5.5 volts and 0 -70C temperature VALUE Typ
CHARACTERISTIC
LOW LEVEL INPUT VOLTAGE TTL Inputs CMOS Inputs (IBTTL1/IBTTL2) (IBCMOS1/IBCMOS2)
SYM
VIL
Min
Max
UNIT
V
CONDITIONS
0.6 0.2VDD VIH 2.2V 0.75VDD V VT+ VTVT+ VTIIN 0.50 1.00 2.00 20.00 1.00 2.00 4.00 75.00 1 2 4 8 250 1.9 1.2 1.3 0.8 VIL to VIH VIH to VIL VIL to VIH VIH to VIL VDD =3V V
HIGH LEVEL INPUT VOLTAGE TTL Inputs CMOS Inputs (IBTTL1/IBTTL2) (IBCMOS1/IBCMOS2)
INPUT HYSTERESIS (IBST1) Rising Falling (IBST2) Rising Falling INPUT CURRENT/RESISTANCE (CMOS / TTL INPUTS) No Resistor Inputs with 1Kohm Resistors Inputs with 2Kohm Resistors Inputs with 4Kohm Resistors Inputs with 75Kohm Resistors Resistor values nominal - See note 1 HIGH LEVEL OUTPUT VOLTAGE All outputs Smallest drive cell OP1/OPT1/OPOS1 Low drive cell OP2/OPT2/OPOS2 Standard drive cell OP3/OPT3/OPOS3 Medium drive cell OP6/OPT6/OPOS6 Large drive cell OP12/OPT12/OPOS12 LOW LEVEL OUTPUT VOLTAGE All outputs Smallest drive cell OP1/OPT1/OPOD1 Low drive cell OP2/OPT2/OPOD2 Standard drive cell OP3/OPT3/OPOD3 Medium drive cell OP6/OPT6/OPOD6 Large drive cell OP12/OPT12/OPOD12 TRISTATE OUTPUT LEAKAGE CURRENT Tristate, open drain and open source output cells OUTPUT SHORT CIRCUIT CURRENT Standard outputs OP3/OPT3/OPOD3 (See note 2) OP3/OPT3/OPOS3 OPERATING SUPPLY CURRENT (per gate) (see note 3) INPUT CAPACITANCE OUTPUT CAPACITANCE BIDIRECTIONAL PIN CAPACITANCE
A K K K K
VIN = VDD or VSS
VOH 0.75VDD 0.75VDD 0.75VDD 0.75VDD 0.75VDD VOL VSS + 0.05 0.2 0.2 0.2 0.2 0.2 0.4 0.4 0.4 0.4 0.4 VDD - 0.05 0.9VDD 0.9VDD 0.9VDD 0.9VDD 0.9VDD
V IOH = -1A IOH = -1mA IOH = -2mA IOH = -3mA IOH = -6mA IOH = -12mA V IOL = 1A IOL = 1mA IOL = 2mA IOL = 3mA IOL = 6mA IOL = 12mA A mA 67 37 135 75 1 5 5 7 270 150 A/MHz pF pF pF ANY INPUTS (Note 4) ANY OUTPUT (Note 4) ANY I/O PIN (Note 5) VDD = MAX, VOUT = VDD VDD = MAX, VOUT = 0V
IOZ IOS
-1
1
VOUT = VSS or VDD
IDDOP CI COUT CVO
Note 1: If resistors are used with outputs the correct value of the resistor must be used to maintain VOL/VOH logic levels. Note 2: Standard driver output OP3 etc. Short circuit current for other outputs will scale. Not more than one output may be shorted at a time for a maximum duration of one second. Note 3: Excluding peripheral buffers. Note 4: Excludes package leadframe capacitance or bidirectional pins. Note 5: Excludes package.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Input Output Voltage Voltage Voltage MIN - 0.5 - 0.5 - 0.5 MAX 7.0 VDD+0.5 VDD+0.5 UNITS V V V
RECOMMENDED OPERATING LIMITS
PARAMETER Supply Voltage Input Voltage Output Voltage Current per pad MIN 3.0 VSS VSS MAX 5.5 VDD VDD 100 UNITS V V V mA
Operation above these absolute maximum ratings or prolonged periods above the recommended operating limits may permanently damage device characteristics and may affect reliability. Storage Temperature: Ceramic Plastic
Operating Temperature: Commercial Grade 0 Industrial Grade -40 Military Grade -55
70 85 125
degree C degree C degree C
-65 - 40
150 125
degree C degree C
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CLA70000V
DESIGN TOOLS
The focus of the GEC Plessey design tool methodology is that of maintaining an open CAD system with all interfaces standardized via EDIF 2.0 . This enables us to provide full support for a variety of 3rd party ASIC design tools and facilitates rapid updating of associated libraries. It also provides an interface to the GEC Plessey (PDS2) design system, which offers a total design environment including behavioral and functional level modelling.
PDS2 - THE GPS ASIC DESIGN SYSTEM
s s s s Behavioral, Functional, and Gate Level Modelling VHDL and Third Party Links Supports Hierarchical Design Techniques EDIF 2.0 Interface PDS2 runs on Digital Equipment computers and is self configuring according to the available machine resources. It comprises design capture (schematic capture or VHDL), testability analysis, logic simulation, fault simulation, auto place and route, and back annotation. The system offers full support for hierarchical design techniques, maintained from design capture through to layout, as well as advanced design management tools. PDS2 may be used either at a GPS Design Center or under licence at the customer's premises. A three day training course is available for first time users.
PDS2 is GPS's own proprietary ASIC design system. It provides a fully-integrated, technology independent VLSI design environment for all GPS CMOS SemiCustom products.
THIRD PARTY SOFTWARE SUPPORT
s Design Kits for major industry standard ASIC design software tools All libraries include fully detailed timing information EDIF 2.0 Interface Post layout back annotation available
Schematic Symbols WORKSTATION ENVIRONMENT PDS ENVIRONMENT
s s s
Schematic Capture
ERC & Netlist Translation Back Annotation
MLE Place & Route
CLA Libraries
Simulation Models
Design Verification
Simulation
GPS supports a wide range of third party design tools including IKOS, Mentor, Verilog, and Viewlogic. The design kits offer fully detailed timing information for all cell libraries, netlist extraction utilities, and post layout back annotation capability where applicable. An example of a workstation design flow is shown in the figure 5 (opposite). Please contact your local GEC Plessey Semiconductor's sales office for further information about support of particular tools.
Test Vector Generation
Vector Translation Test Program Generation
Figure 5 : Workstation Design Flow
DESIGN SUPPORT
Design support is available from various centres worldwide each of which is connected to our Headquarters via high speed data links. A design centre engineer is assigned to each customers circuit, to ensure good communication, and a smooth and efficient design flow. As part of the design process GPS operates a thorough design audit procedure to verify compliance with customer specification and to ensure manufacturability. The procedure includes four separate review meetings, with the customer, held a key stages of the design. The standard design audit procedure is outlined opposite. Review 1: Held at the beginning of the design cycle to check and agree on specifications and design timescales. Held after Logic Simulation and prior to Layout. Checks to ensure satisfactory functionality, timing performance, and adequate fault coverage Held after Layout and Post layout Simulation. Verification of design performance after insertion of actual track loads. Final check of all device specifications before prototype manufacture. Held after prototype delivery. Confirms that the devices meet the specification and are suitable for full scale production.
Review 2
Review 3
Review 4
5
CLA70000V
PACKAGING
Production quantities of the CLA70000 family are available in industry-standard ceramic and plastic packages according the codes shown below. Prototype samples are normally supplied in ceramic only.
DC DG DP AC AC (P) MP LC HC DILMON CERDIP PLASDIP P.G.A. POWER P.G.A. SMALL OUTLINE (S.O.) LCC LEADED CHIP CARRIER Dual in Line, Multilayer ceramic. Brazed leads Metal Sealed Lid. Through Board. Dual In Line, Ceramic body, Alloy leadframe, Glass Sealed, Through Board. Dual In Line, Copper or Alloy leadframe, Plastic Moulded. Through Board. Pin Grid Array, Multilayer Ceramic. Metal Sealed lid. Through Board. As above with cavity down and Cu/W heat plate. Dual In Line, 'Gullwing' Formed Leads. Plastic Moulded Surface Mount. Leadless Chip Carrier. Multilayer Ceramic. Metal Sealed Lid. Surface Mount. Quad Multilayer Ceramic. Brazed J Formed Leads. Metal Sealed Lid. Surface Mount Quad Multilayer Ceramic. Brazed Leads. Metal Sealed Lid. Surface Mount. As above with cavity down, and Cu/W heat plate. Quad Ceramic Body, `J' Formed Leads. Glass Sealed. Surface Mount. Quad Ceramic Body, `Gullwing' Formed Leads. Glass Sealed. Surface Mount. Quad Plastic Leaded Chip Carrier. `J' Formed Leads. Plastic Moulded. Surface Mount Plastic Quad Flat Pack. `Gullwing' Formed Leads. Plastic Moulded. Surface Mount.
GC GC (P) HG GG HP
LEADED CHIP CARRIER POWER LEADED CHIP CARRIER QUAD CERPAC CERAMIC QUAD FLATPACK PLCC
GP
PQFP
PRIMARY SEMI-CUSTOM DESIGN CENTRES
UNITED KINGDOM: Swindon, Tel: (0793) 518000 Tx: 449637 Fax: (0793) 518411. Oldham, Tel: (061) 682 6844, Fax: (061) 688 7898. Lincoln, Tel: (0522) 500500 Tx: 56380 Fax: (0522) 500550. Wembley, Tel: (081) 908 4111 Tx: 28817 Fax: (081) 908 3801. UNITED STATES OF AMERICA: Scotts Valley, Tel: (408) 438 2900 ITT Tx: 4940840 Fax: (408) 438 5576. Dedham, Tel: (617) 320-9369. Fax: (617) 320-9383. Irvine, Tel: (714) 455-2950. Fax: (714) 455-9671. AUSTRALIA: Rydalmere, NSW, Tel: (612) 638 1888. Fax: (612) 638 1798. FRANCE: Les Ulis Cedex, Tel: (6) 446 23 45 Tx: 602858F. Fax: (6) 446 06 07. ITALY: Milan, Tel: (02) 33001044/45 Tx: 331347 Fax: (GR3) 2316904. GERMANY: Munich, Tel: (089) 3609 06 0 Tx: 523980. Fax: (089) 3609 06 55. JAPAN: Tokyo, Tel: (3) 839 3001. Fax: (3) 839 3005.
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Tx: 449637 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS Sequoia Research Park, 1500 Green Hills Road, Scotts Valley, California 95066, United States of America. Tel (408) 438 2900 ITT Telex: 4940840 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES * FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Tx: 602858F Fax : (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Tx: 523980 Fax : (089) 3609 06-55 * ITALY Milan Tel: (02) 33001044/45 Tx: 331347 Fax: (GR3) 316904 * JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228 * NORTH AMERICA Integrated Circuits, Scotts Valley, USA Tel (408) 438 2900 ITT Tx: 4940840 Fax: (408) 438 7023. SOS, Microwave and Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061. * SOUTH EAST ASIA Singapore Tel: 2919291 Fax: 2916455 * SWEDEN Johanneshov Tel: 46 8 7228690 Fax: 46 8 7227879 * UNITED KINGDOM & SCANDINAVIA Swindon Tel: (0793) 518510 Tx: 444410 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1992 Publication No. DS 3535 Issue No. 1.0 August 1992
This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of any product or service.
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